A system on chip (SoC) (e.g., a field programmable gate array (FPGA), a programmable logic device (PLD), or an application specific integrated circuit (ASIC)) can contain a packet network structure known as a network on a chip (NoC) to route data packets between logic blocks in the SoC—e.g., programmable logic blocks, processors, memory, and the like. Although the NoC can be formed from programmable logic, this requires a lot of area on the SoC which could be used for other features or circuitry (e.g., more processors, memory, or available programmable logic for the user). Hardening all, or some, of the NoC (e.g., using non-programmable circuitry) can significantly reduce its footprint in the SoC but the NoC then loses flexibility. That is, the hardened components in the NoC cannot be reconfigured to support different communication protocols.